The present invention relates generally to semiconductor chip fabrication.
Increasing semiconductor chip density has placed more components on the wafer surface, which has, in turn, decreased the area available for surface wiring of the components. This has led to multilevel metallization schemes using a stack of multiple metal layers on the wafer. A typical stack starts with a barrier layer formed by silicidation of the silicon surface to produce a lowered electrical resistance between the surface and the metal layer.
Barrier layers also prevent alloying of aluminum and silicon if aluminum is the conducting material of the metal layer. Both titanium-tungsten (TiW) and titanium nitride (TiN), as well as other materials, are typically used to form a barrier layer.
Sometimes a first layer of platinum silicide is formed on the exposed silicon before the TiW is deposited. TiW is usually sputter-deposited onto the wafer into the open contacts before the conducting material deposition (i.e., aluminum) takes place. The TiW deposited on the field oxide is normally removed from the surface during the aluminum etch step.
Titanium nitride layers can be placed on the wafer by several deposition techniques, including evaporation, and sputtering. A layer of titanium is normally required under TiN films to provide a high conductivity intermediate with silicon substrates.
With copper (Cu) metallization, the barrier is also critical. Copper inside the silicon ruins device performance. Barrier metals frequently used include TiN, tantalum (Ta), and tantalum nitride (TaN).
A typical wafer has a layer of some dielectric material, called an intermetallic dielectric layer (xe2x80x9cIDLxe2x80x9d), that provides the electrical isolation between metal layers. This layer may receive a masking step that etches new-contact holes, called xe2x80x9cviasxe2x80x9d or xe2x80x9cplugsxe2x80x9d, down to the first-level metal. Conducting plugs may also be created by depositing conducting material into the hole. The first-level metal layer is then deposited and patterned. The IDL/plug/metal deposition/patterning sequence is repeated for subsequent layers.
A multilevel metal system is more costly than a single level metal system. It is also of lower yield and requires greater attention to planarization of the wafer surface and intermediate layers to create good current-carrying leads. It is partly in accordance with this greater attention that processes have been developed to remove contaminating oxide buildup on the wafer (xe2x80x9cnative oxidexe2x80x9d).
Semiconductor wafer fabrication thus involves processes in which one or more layers are formed on a dielectric wafer, often after an interconnect structure has been patterned onto the dielectric (a xe2x80x9chard maskxe2x80x9d). Typically, metal is deposited on the wafer and selectively etched away. Successive layers of metal and semiconductor or dielectric form electrical components on the semiconductor wafer.
Prior to metal deposition, the surface of the wafer may require cleaning of native oxide. Such cleaning is conventionally performed in a separate sputtering chamber from that used for metal deposition. Moving the wafer from one deposition chamber to another incurs an increased chance of contamination of the wafer from the ambient environment, as well as an increase of cost of fabrication, since at least two chambers are required.
Conventional directional argon bombardment (xe2x80x9cAr sputteringxe2x80x9d) is a common process used during deposition of metal barrier and seed layers on an interconnect structure. Ar sputtering processes are used for both metal deposition and as a xe2x80x9ccleanxe2x80x9d.
Sputter deposition is a process that (in general) can deposit any material on any substrate. It is widely used to coat costume jewelry and put optical coatings on glasses and lenses. Sputtering takes place in a vacuum, and is a physical, not a chemical process. It is sometimes also referred to as physical vapor deposition. The foregoing description of sputter deposition is a general description, and is not intended to exclude alternative theories of how the sputtering process operates or any particular sputtering apparatus.
Sputter deposition conventionally takes place inside a vacuum chamber (xe2x80x9cdeposition chamberxe2x80x9d), in which a solid slab, called a xe2x80x9ctargetxe2x80x9d, of the material desired to be deposited. The target is electrically grounded. Argon gas is introduced into the deposition chamber and is ionized to a positive charge. The positively charged Ar atoms (actually xe2x80x9cionsxe2x80x9d) are attracted to the grounded target and accelerate towards it. During the acceleration they gain momentum, which is force, and strike the target. At the target, a phenomenon called momentum transfer occurs. Just as a cue ball transfers its energy to other balls on the pool table, causing them to scatter, the Ar ions strike the slab of deposition material, causing its particles to scatter. Thus, the Ar atoms xe2x80x98knock offxe2x80x99 atoms and molecules from the target into the vacuum of the deposition chamber. This is the sputtering activity. The sputtered atoms or molecules scatter in the deposition chamber with some coming to rest on the wafer.
Sputtering is a favored method of depositing material on a wafer in a stepwise fashion, where an even coating is desired. Material arrives at the wafer with a wide range of angles to coat the wafer surface. Such xe2x80x9cstepxe2x80x9d coverage is further improved by rotating and heating the wafer.
Clean and dry argon (or neon) is required to maintain film (coating) composition characteristics, and low moisture is required to prevent unwanted oxidation of the deposited film. The deposition chamber is loaded with the wafers and the pressure is reduced by pumps (pumped down) to approximately 1xc3x9710xe2x88x929 torr. The Ar is introduced and ionized. Control of the Ar amount entering the chamber is critical due to its effect of raising the pressure in the chamber. With the Ar and sputtered material in the deposition chamber, the pressure is raised to approximately 1xc3x9710xe2x88x923 torr. Chamber pressure is a critical parameter in the deposition rate of the system. Thus, deposition chambers are precision equipment with associated high costs of purchase, operation and maintenance. Also, most conventional deposition chambers require careful and time-consuming setup and operations.
The intention of conventional Ar sputter clean is to remove the native oxide on the surface of the wafer to which metal will be deposited. The Ar sputter clean may, however be performed on patterned dielectric or metals layers. It was observed that the bombardment of an Ar sputter clean always results in some potential problems.
When conventional Ar sputter clean is performed on a patterned wafer, damage may occur to the wafer. In FIG. 2, a profile view schematic of a wafer, before 200 and after 200xe2x80x2 conventional Ar sputter clean is presented. The wafer 200, 200xe2x80x2 includes several features. It includes a hard mask 201, and IDL 202, and a metal 203. After conventional Ar sputter clean, the wafer 200xe2x80x2 may have damage to the hard mask 201xe2x80x2, or to the IDL 202xe2x80x2. Changes may also occur to the etching profile 204xe2x80x2, as well as to the sidewalls 206xe2x80x2. Moreover, the underneath metal may be splashed onto and even penetrate the IDL 205xe2x80x2.
Damage may also occur to the wafer when conventional Ar sputter clean is performed on a metal layer. In FIG. 3(a) an exemplary profile schematic of a wafer, before (300) and after (300xe2x80x2) performing conventional Ar sputter clean, is presented. The wafer 300, 300xe2x80x2 includes a hard mask 301, and IDL 302, and a metal 303. After conventional Ar sputter clean, the wafer 300xe2x80x2 may have deposited metal removed at the field 307xe2x80x2, trench bottom 302xe2x80x2 and tapered sidewall 306xe2x80x2. Damage to the hard mask 301xe2x80x2 or to the IDL 302 may also occur, as well as changes to the etching profile 304xe2x80x2. Again, the underneath metal may be splashed onto the IDL and onto the deposited metal 305xe2x80x2.
A need exists for a process of semiconductor fabrication that minimizes the number of process chambers used by not requiring the use of more than one chamber for the metal deposition and sputter clean processes.
A need exists for a gaseous sputter clean process to be performed on a dielectric layer which avoids or minimizes damage to the hard mask, or to an IDL, and that does not significantly change the etching profile or splash underneath metal onto the IDL.
The present invention provides a method of fabricating a semiconductor device within a single deposition chamber, the semiconductor device being a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques. Initial metal layer(s) may or may not be deposited on the patterned dielectric structure. Next, without moving the patterned wafer to a sputtering chamber, native oxide is removed by a directional gaseous bombardment, which comes simultaneously with a deposition of metal neutral.
The method further preferably includes deposition of one or more initial metal layers on the dielectric structure with a thickness in the range 10 Angstroms to 500 Angstroms.
In accordance with an embodiment, one or more further materials may be deposited on the dielectric structure. These materials may preferably include liner or seed layer materials, such as any one or more materials selected from the group comprising TaN, Ta, Ti, Ti(Si)N, W or Cu.
A need also exists for a gaseous sputter clean process to be performed on a metal layer which avoids or minimizes damage to the hard mask or to an IDL, that does not significantly change the etching profile, that minimizes removal of deposited metal at the field, trench bottom and tapered sidewall, does not splash the underneath metal onto the IDL and onto the deposited metal, and does not require that the semiconductor structure be moved to a process chamber different from that used for earlier fabrication steps.
The present invention advantageously provides a method of in situ deposition of a metal neutral for protecting the structure features during the directional gaseous bombardment for removing native oxide on a metal surface of a semiconductor device. Directional gaseous bombardment of the semiconductor device with simultaneous metal neutral deposition is preferably used.
In a preferred embodiment, the metal neutral may include the same material as the target or other materials selected from the group consisting of Ta, Ti or W.